The basic unit of information for storage and retrieval in digital systems is the data bit, a binary number having a value of zero or one. A data bit in a digital system has logic states of "high" and "low," often corresponding to a physical parameter such as the voltage at a node in a circuit. Information stored in semiconductor circuits is quantified in terms of the number of bits stored. These circuits, collectively called memory devices, include latches, flip-flops, registers, and memories depending to some extent on the number of bits stored. However, the fundamental circuit for storing a data bit, herein called a memory cell, is the common building block from which latches, flip-flops, registers, memories, and the like are made.
Several common circuits have been used for the memory cell in the various types of memory devices. Some devices including dynamic random access memory (DRAM) employ a memory cell circuit having one transistor and one capacitor. The DRAM cell provides one signal for stored data. Other devices including the static random access memory (SRAM) employ a memory cell circuit having primarily a cross coupled pair of transistors. The SRAM cell provides two complementary signals for stored data. For example, when the signals are respectively D and D*, a zero is represented when D is low and D* is high, and a one is represented when D is high and D* is low. Other combinations of D and D* are undefined; that is, they serve no purpose in the memory device.
Memory devices that are used for storing many bits of information provide an output data signal in response to an input address signal during a "read" operation called a read cycle. In a complex memory device, the read operation may be performed as a process of selecting, sensing, and outputting the content of memory cells. The duration of such a process is called the access time. Complex memory devices may have several types of operations distinguished by control signals including read/write, address strobes, programming and erasure strobes, transfer enable, and output enable signals. The read cycle begins when the operation is defined by these control signals and an address is specified on the address input of the memory device.
The address can be specified in one of several ways depending on the design of the memory device. For example, an address can be specified serially in conjunction with a clock signal or in parallel with a strobe signal. A combination of these methods could be used, for example, by presenting on 16 parallel address lines a 32-bit address in two steps accompanied by upper and lower address strobes. In a conventional DRAM, these strobes are associated with the row and column organization of memory cells in an array. Designs for high density memory devices employ several arrays of cells having minute dimensions. Typically, the signal or signals representing the data bit in a memory cell are weak.
The read cycle concludes with presentation of signals for use outside the memory device that represent the data addressed. The weak signal levels internal to the memory device are sensed and amplified. Amplified signals at internal signal levels are then translated to conventional logic levels and gated onto the output terminals of the memory device. The level translation and gating are accomplished by an output buffer circuit. When the output buffer is supplying a signal on the output terminal, it is said to be gated on, or enabled; otherwise it is off or disabled.
Memory circuit timing is critical to the efficiency of many systems applications for memory devices. In a computer system, for example, the processor and memory devices are connected by a signal path called a bus. The bus is used for information flow between the processor and other devices connected thereto. One measure of system efficiency is the extent of time the bus is idle or unusable. The bus is "idle" when it is not being used by any device. The bus is "unusable" when it is dedicated to a device but the signal on the bus is invalid, conveying no useful information.
Conventional DRAM devices used in computer systems allow the output buffer to provide spurious signals on the bus causing the bus to be unusable for a period of time. This problem is described in terms of DRAM devices in a computer system, but exists in other applications and with other types of memory devices. For the DRAM application, the bus is unusable for a time preceding output of valid data. A read cycle begins when the row address strobe (RAS*) falls (a high to low transition) at a time when the address input specifies the row address. When the column address is specified on the address input, the column address strobe (CAS*) falls. Conventionally, the output buffer is enabled a short delay after CAS* falls and before data can be guaranteed to be valid. Hence, spurious signals can appear on the bus, and consequently other uses of the system bus must wait until the memory device is no longer dedicated to the bus, and power is wasted while driving spurious signals to conventional logic levels.
In other conventional memory devices including DRAM and video random access memory (VRAM) devices, read operations have a so-called "page mode" wherein a row address is specified for use with several subsequently specified column addresses. Column address changes are detected by a circuit that provides a timing pulse. The timing pulse enables the output buffer after a fixed predetermined delay. The delay may be too short for some memory cells and sense amplifiers that respond relatively slowly due to physical location or circuit element variations caused by fabrication process variations. In such a case, the output buffer is enabled (upon the expiration of the delay) at a time when spurious signals exist on the data path. If the delay is long enough to avoid all spurious signals, data from faster cells will wait at the output buffer before the buffer is enabled. A faster access time would have been possible had the delay been shorter.
Some conventional memory devices perform back to back read operations. In such a device, a subsequent read cycle immediately follows latching previously read data in the output buffer. A timing pulse operates the latch after a fixed predetermined delay. In some devices, column address changes are detected by a circuit that provides the timing pulse. The delay must be designed to allow for the precharge, address decoding, sensing, and driving required for the longest read operation in order to guarantee that the latched data represents the content or the memory and not spurious signals preceding the memory content signal. When the delay is long enough to avoid all spurious signals, data from faster cells wait at the output buffer before the latch is enabled. A faster access time would have been possible had the delay been shorter.
DRAM or VRAM devices designed to enable the output buffer after a fixed predetermined delay cannot be effectively sorted by access time. When many devices are manufactured on a single wafer, the predetermined delay must be long enough to account for process variation. For example, if the delay is long enough to guarantee operation of all devices on the wafer, the performance of some of the devices is limited by the delay. These devices could have been sorted and guaranteed at a faster access time than the access time of other devices on the same wafer. Memory devices guaranteed at a faster access time command a higher market price and facilitate new and improved systems from integrated microprocessors to automated equipment.
Thus, there remains a need for a memory device whose output buffers do not output spurious signals. In addition, there remains a need for an improved method for reading a memory cell without dependence on predetermined delays. Further improvement in performance of systems using memory devices can be gained by employing methods of the present invention and incorporating circuits of the present invention in the design of memory devices.